Anti-SEE (single event effect) protection is vital for integrated circuits (ICs) such as those operating in outer space, and is becoming critical for ground-based circuits due to increasing miniaturization of their components. In integrated circuits (ICs) such as current-mode logic (CML) and similar ICs with a current-switching architecture, single-event effects (SEE) are associated with strikes of energetic particles. These strikes cause an electric charge to be generated in the IC's regions resulting in the appearance of short current pulses flowing into the heterojunction bipolar transistor's (HBT) collector node and out of its base, emitter, and substrate nodes.
FIG. 1 shows a model of a SEE in a heterojunction bipolar transistor (HBT) derived from G. Niu, R. Krithivasan, J. Cressler et al., “A Comparison of SEU Tolerance in High-Speed SiGe HBT Digital Logic Designed with Multiple Circuit Architectures,” IEEE Trans. On Nuclear Science, v. 49, No. 6, December 2002, pp. 3107-3114. The equivalent circuit shown in FIG. 1 describes three independent current sources iBp, iSp, and iEn, which represent SEE-induced transient current pulses through the base, substrate, and emitter nodes correspondingly. The SEE-induced collector current iCn is then given by iCn=−(iBp+iSp+iRn).
A computer simulation of these current pulses in a silicon germanium (SiGe) HBT with a 0.2×0.72 μm2 emitter area for a linear energy transfer (LET)=20 pC/μm is shown in FIG. 2. As can be seen, the collector and emitter currents run into the nodes, while the base and emitter currents are reversed. It is important to note that the collector current pulse is significantly higher than the base current pulse. Assuming a certain resistive termination at the collector, emitter, and base nodes, the described behavior results in a lower collector node voltage and a higher base node voltage. The changes in the emitter node voltage depend on the actual termination scheme.
There exist several techniques for anti-SEE protection including (i) triple majority voting described by R. Katz, R. Barto, P. McKerracher, B. Carkhuff, and R. Koga, in “SEU Hardening of Field Programmable Gate Arrays for Space Applications and Device Characterization” (unabridged version), IEEE Transactions on Nuclear Science, NS-41, pp. 2179-2186, July 1994, and by David Fulkerson, in “SEU Hard Majority Voter for Triple Redundancy”, U.S. Pat. No. 6,667,520, Dec. 23, 2003, (ii) a dual interleave cell (DICE) architecture described by T. Calin, M. Nicolaidis, and R. Velazco, in “Upset hardened memory design for submicron CMOS technology,” IEEE Trans. Nucl. Sci., vol. 43, pp. 2345-2352, December 1996, and by Jerry Dooley, in “SEU-Immune Latch for Gate Array, Standard Cell, and other ASIC Applications,” U.S. Pat. No. 5,311,070, May 10, 1994, (iii) a temporal latch architecture described by D. G. Mavis and P. H. Eaton, in “Temporally Redundant Latch for Preventing Single Event Disruptions in Sequential Integrated Circuits,” U.S. Pat. No. 6,127,864, October 2000., (iv) a current-sharing architecture described by M. P. LaMacchia and W. O. Mathes, in “SEU Hardening Approach for High Speed Logic,” U.S. Pat. No. 5,600,260, and by Paul W. Marshall, Martin A. Carts, Arthur Campbell, Dale McMorrow, Steve Buchner, Ryan Stewart, Barbara Randall, Barry Gilbert, and Robert A. Reed, in “Single Event Effects in Circuit-Hardened SiGe HBT Logic at Gigabit per Second Data Rates,” IEEE Transactions on Nuclear Science, vol. 47, No. 6, December 2000, pp. 2669-2674, and (v) a gated feedback latch architecture described by Ramkumar Krithivasan et al., in “Application of RHBD Techniques to SEU Hardening of Third-Generation SiGe HBT Logic Circuits,” IEEE NSREC, Ponte Vedra Beach, Fla.; Jul. 17-21, 2006.
Only the last two architectures are really suitable for very high-speed applications based on HBTs. It has been shown by G. Niu, R. Krithivasan, J. Cressler et al. cited above that a current-sharing architecture cannot provide the required Anti-SEE protection (ASP) in CML latches. CML latches are the most commonly used cells in digital designs. Thus, a current-sharing architecture cannot be considered a universal approach to the protection of CML cells.
In some respects, the gated feedback latch architecture shown in FIG. 3 is arguably the closest approach to the techniques proposed herein. The latch comprises two pass cells 10 and 20, two storage cells 30 and 40, and two OR gates 50 and 60 implemented as emitter followers. The two pass cells 10 and 20 have two differential data inputs 11/12 and 21/22, respectively. The two storage cells 30 and 40 are provided with feedback through the OR gates 50 and 60.
The gated feedback latch architecture of FIG. 3 provides anti-SEE protection for the HBTs of the pass cells 10 and 20 in case of completely independent data inputs. However, the gated feedback latch architecture of FIG. 3 has several drawbacks. For example, a SEE in any of the storage cell HBTs results in unrecoverable distortion of the corresponding data output voltages 91/92 due to the base current pulse described above. Also, a SEE in any of the HBTs of the OR-gates 50 and 60 results in an erroneous change of state in the storage cells 30 and 40 when operating in the storage mode. Further, a SEE in any of the tail current sources 70 and 80 results in significant distortion of the output signals, as well as a disturbance of the reference voltage 90, which propagates to all cells connected to the same reference node. Additionally, the gated feedback latch architecture of FIG. 3 is actually an emitter-coupled logic (ECL) architecture that utilizes emitter followers for driving both top-level and bottom-level inputs. As a result, ECL gates require higher supply voltages and consume significantly higher power compared to similar CML gates.